The invention relates to a bottom-gate thin film transistor having a silicide gate.
Walker et al., U.S. patent application Ser. No. 10/335,089, “Method for Fabricating Programmable Memory Array Structures Incorporating Series-Connected Transistor Strings,” filed Dec. 31, 2002, hereinafter the '089 application and hereby incorporated by reference, describes a monolithic three dimensional memory array of charge storage transistors having stacked memory levels. This arrangement of stacked memory cells results in a high-density nonvolatile memory array.
Fabrication of the memory array of the '089 application, however, presents considerable challenges, for example in photolithography and etch processes. There is a need, therefore, for a charge storage memory cell that is easily fabricated in a monolithic three dimensional memory array.